The present invention relates to a CCD (Charge Coupled Device) image sensor, and more particularly to an interline transfer CCD image sensor.
In general, an interline transfer CCD image sensor is formed on a plane to be corresponded with 1:1 for a photodetection sensor and a signal transfer region, and is applied to a household system, such as a television receiver or a cam-coder, which comparatively does not require a high degree of image stability, rather than to broadcasting equipment or military equipment, which do require a high degree of image force or stability.
With reference to FIG. 3 through FIG. 6, a conventional interline transfer CCD image sensor will be described below.
Hereinafter, each of the odd numbered horizontal lines, in which the photodiodes 31 are arranged, are referred to as an odd horizontal line, and each of the even numbered horizontal lines are referred to as an even horizontal line.
FIG. 3 shows a block diagram of a conventional interline transfer CCD image sensor. Each photodiode 31 is respectively connected to a corresponding buried channel VCCD (Vertical Charge Coupled Device) region 32 so as to transfer an image signal charge to the VCCD region 32 in one direction only. Each VCCD region 32 is operatively connected to an HCCD (Horizontal Charge Coupled Device) 33, to simultaneously transfer image signal charges transferred from each photodiode 31 to the HCCD by a conventional four phase clocking operation in accordance with 1st through 4th clock signals V.sub..phi.1 .about.V.sub..phi.4.
Further, an output gate 34, a floating diffusion region 35, a reset gate electrode 36 and a reset drain 37 are connected in turn to the output side of the HCCD region, and a sense amplifier 38 is connected to the floating diffusion region 35.
FIG. 4 shows a portion of a layout diagram of the CCD image sensor of FIG. 3. A channel stop region 39 is formed between VCCD region 32 and photodiode 31. Odd gate electrode 40, which is connected to receive first and second VCCD clock signals V.sub..phi.1 .about.V.sub..phi.2, is formed on the upper side of channel stop region 39 and VCCD region 32, to connect to each transfer gate 41 of the photodiodes 31 arranged on the odd horizontal line. Even gate electrode 42, which is connected to receive third and fourth VCCD clock signals V.sub..phi.3 .about.V.sub..phi.4, is formed on the upper side of the VCCD region 32 to connect to each transfer gate 43 of the photodiodes 31 arranged on the even horizontal line.
Since odd gate electrode 40 and even gate electrode 42 must be the same type, they can be successively, repeatedly formed, and odd gate electrode 40 and the even gate electrode 42 are electrically isolated through insulating material (not shown).
Further, each transfer gate 41, 43 and each odd and even gate electrode 40, 42 is formed from polysilicon material. Odd gate electrode 40 is formed at the lower side and at the upper side of the photodiode 31 of the odd horizontal line, and consists of the second odd gate electrode 40b connected to each transfer gate 41 of the photodiode 31, to which is applied the first VCCD clock signal V.sub..phi.1, and formed at each odd horizontal line.
The even gate electrode 42 is formed at the lower side and at the upper side of the photodiodes 31 of the even horizontal line. The first gate electrode 42a, which is connected to receive the fourth VCCD clock signal V.sub..phi.4, and which consists of the second even gate electrode 42b, connected to the transfer gate 43 of the photodiodes 31, which connected to receive the third VCCD clock signal V.sub..phi.3, and formed at each even horizontal line.
Further, the two fields, designated as even and odd are generated by the first through the fourth VCCD clock signals V.sub..phi.1 .about.V.sub..phi.4. The operation of the clocking of the VCCD region will be discussed later herein in detail.
FIG. 5 shows a cross-sectional view taken along the line a-a' of FIG. 4. A p type well 45 is formed on the n type substrate 44. The n type VCCD region 32 of the n type photodiodes 31, forming the even horizontal line, is successively arranged in a predetermined interval and in a connected shape through the channel stop region 39. The transfer gate 43, for transferring the charge, is formed above the upper side of well 45 between and above each photodiode 31 and each corresponding VCCD region 32. The second even gate electrode 42b, which is connected to receive the 3rd VCCD clock signal V.sub..phi.3, is formed at the upper side of each VCCD region 32 to connect to each transfer gate 43 of the photodiodes 31 of the even horizontal line.
The p.sup.+ type thin film 46 is formed on the surface of each photodiode 31 to ordinarily apply the initial bias. The conventional interline transfer CCD image sensor is operated as follows.
The image sensor charge generated at the photodiodes 31 by the VCCD clock signal voltage applied to the gate electrode 42 of FIG. 5, is transferred to the VCCD region, and successively is transferred to the HCCD region 33 shown in FIG. 3. At this time, the potential contour out of the VCCD region 32 is changed, as shown in FIG. 6, with the potential contour of the line b-b' of FIG. 5. Namely, in FIG. 6, it is known that the potential contour is gradually brought down when the VCCD clock signal voltage is reduced from the voltage V.sub.1 to the V.sub.5.
However, it is known that the potential contour of the VCCD region is not reduced further even though the voltage of the VCCD clock signal is reduced to less than the voltage V.sub.3, as shown in FIG. 6, because the p type well 45 of FIG. 5 is connected to receive a OV voltage by connection to ground bias as is channel stop region 39. Here, the voltage magnitude at which point the potential contour is not reduced further, is ordinarily called the pinning voltage (Vp: Pinning Voltage).
Consequently, the conventional interline transfer CCD image sensor shown in FIG. 5, even though the VCCD clock signal voltage is actually reduced less than the voltage V.sub.3,V.sub..phi.1, this negative voltage is only applied to the insulation film (not shown, but formed between the surface of VCCD region 32 and the gate electrode 42) and has no effect in the VCCD region 32.
Ultimately, the controlling extent is narrow for controlling the transfer efficiency of the image signal charge out of the VCCD region in accordance with need of the user.
The conventional art as above cannot reduce the pinning voltage, even though a large negative voltage is applied to the gate electrode, because the pinning voltage is only determined by the VCCD output signal. Therefore, since the transfer width of the potential contour out of VCCD region has this limitation, the storage capacity of the image signal charge and the efficiency of the charge transfer cannot be maximized.
The above conventional art is discussed in an article entitled A Very Small "Super-8 Format CCD Imager for a Single-Chip Color Camera" published at page 1446 of the IEEE Transaction on Electron Devices, VOL. 38, NO. 5, in May 1991.